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SI5017
OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
Features
High-speed clock and data recovery device with integrated limiting amplifier: Supports OC-48/STM-16 and Loss-of-signal level alarm 2.7 Gbps FEC Data slicing level control DSPLL(R) technology 10 mVPP differential sensitivity Jitter generation 3.0 mUIrms (typ) 3.3 V supply Small footprint: 5 x 5 mm Reference and reference-less operation supported Ordering Information: See page 22.
Applications
SONET/SDH/ATM routers Add/drop multiplexers Digital cross connects Board level serial links SONET/SDH test equipment Optical transceiver modules SONET/SDH regenerators Pin Assignments SI5017
BER_ALM CLKOUT+ DIN- CLKOUT- 21 VDD 20 REXT 19 RESET/CAL 18 VDD 17 DOUT+ 16 DOUT- 15 TDI 8 LTR 9 LOS 10 11 12 13 14 DSQLCH DIN+ VDD VDD CLKDSBL BER_LVL VDD
Description
The SI5017 is a fully-integrated, high-performance limiting amplifier (LA) and clock and data recovery (CDR) IC for high-speed serial communication systems. It derives timing information and data from a serial input at OC-48 and STM-16 rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ forward error correction (FEC). Use of an external reference clock is optional. Silicon Laboratories DSPLL(R) technology eliminates sensitive noise entry points, thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The SI5017 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (-40 to 85 C).
VDD VDD LOS_LVL SLICE_LVL REFCLK+ REFCLK- LOL 1 2 3 4 5 6 7
NC
28 27 26 25 24 23 22
GND Pad
Functional Block Diagram
LOS_LVL LOS
Signal Detect Retim er
DSQLCH BUF
2
DOUT+ DOUT-
DIN+ DIN-
2
Lim iting Am p
DSPLL
BER Monitor
BUF
2
CLKOUT+ CLKOUT- CLK_DSBL
REFCLK+ REFCLK- (Optional)
2
Lock Detection Bias Gen.
Reset/ Calibration
BER_ALM REXT RESET/CAL
SLICE_LVL
LTR
BER_LVL
LOL
Rev. 1.4 10/05
Copyright (c) 2005 by Silicon Laboratories
SI5017
SI5017
2
Rev. 1.4
SI5017 TABLE O F CONTENTS
Section Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.2. DSPLL(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3. Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4. Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.5. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.6. Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7. Loss-of-Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.8. Bit-Error-Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.9. Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.10. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.11. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.12. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.13. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.14. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.15. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.16. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.17. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.18. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Pin Descriptions: SI5017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3
Rev. 1.4
SI5017
1. Detailed Block Diagram
LOS BER_LVL BER_ALM LTR DSQLCH
LOS_LVL
Signal Detect
BER Monitor Retime
DOUT+ DOUT-
DIN+
Limiting Amp
Phase Detector
A/D
DSP n
VCO
CLK Dividers
CLKOUT+ CLKOUT-
DIN+
SLICE_LVL
Slicing Control Lock Detection
CLKDSBL
REFCLK (optional) Bias Generation
LOL
REXT
Calibration
RESET/CAL
4
Rev. 1.4
SI5017
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature SI5017 Supply Voltage2 Symbol TA VDD Test Condition Min1 -40 3.135 Typ 25 3.3 Max1 85 3.465 Unit C V
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated. 2. The SI5017 specifications are guaranteed when using the recommended application circuit (including component tolerance) of the "Typical Application Schematic" on page 11.
V SIG NAL+ SIG NAL- V IS
t A. Operation with Single-Ended Inputs V SIGNAL+ SIGNAL- 0.5 V ID
(SIGNAL+) - (SIG NAL-)
V ID t
B. O peration with Differential Inputs and Outputs
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t Cf-D DOUT t C r-D
CLK OUT
Figure 2. Clock to Data Timing
Rev. 1.4
5
SI5017
80% 20% tF tR
DOUT, CLKOUT
Figure 3. DOUT and CLKOUT Rise/Fall Times
taq RESET/Cal
LOL
DATAIN
LOL taq
Figure 4. PLL Acquisition Time
DATAIN
LOS Threshold Level
LOS tLOS
Figure 5. LOS Response Time
6
Rev. 1.4
SI5017
Table 2. DC Characteristics
(VDD = 3.3 V 5%, TA = -40 to 85 C)
Parameter
Symbol Test Condition
1
Min
Typ
Max
Unit
Supply Current FEC (2.7 Gbps) OC-48
IDD
-- -- -- -- See Figure 11 See Figure 10 See Figure 1A See Figure 1B See Figure 1A See Figure 1B Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line Single-ended 1.30 1.90 10 10 200 200 84 700 700 1.6 1.6 84 -- 2.0 -- -- 9 50 IO = 2 mA IO = 2 mA -- 2.0
173 170 571 561 1.50 2.10 -- -- -- -- 100 800 800 1.95 1.80 100 -- -- -- -- -- 100 -- --
184 180 637 623 1.62 2.30 500 1000 750 1500 116 1000 1100 2.35 2.35 116 .8 -- 10 10 -- 125 0.4 --
mA
Power Dissipation FEC (2.7 Gbps) OC-48 Common Mode Input Voltage (DIN)2 Common Mode Input Voltage (REFCLK)2 DIN Single-ended Input Voltage Swing DIN Differential Input Voltage Swing2 REFCLK Single-ended Input Voltage Swing REFCLK Differential Input Voltage Swing2 Input Impedance (DIN) Differential Output Voltage Swing (DOUT) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (DOUT) Output Common Mode Voltage (CLKOUT) Output Impedance (DOUT,CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Input Impedance (LVTTL Inputs) LOS_LVL, BER_LVL, SLICE_LVL Input Impedance Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs)
2 2
PD
mW V V mV mV mV mV
VICM VICM VIS VID VIS VID RIN VOD VOD VOCM VOCM ROUT VIL VIH IIL IIH RIN RIN VOL VOH
mVPP mVPP V V
V V A A k k V V
Notes: 1. No load on LVTTL outputs. 2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac coupled to ground.
7
Rev. 1.4
SI5017
Table 3. AC Characteristics (Clock and Data)
(VDD = 3.3 V 5%, TA = -40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Clock Rate Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Output Data Rise Time Output Data Fall Time Clock to Data Delay FEC (2.7 Gbps) OC-48 Clock to Data Delay FEC (2.7 Gbps) OC-48 Input Return Loss Slicing Level Offset (relative to the internally set input common mode voltage) Loss-of-Signal Range* (peak-to-peak differential) Loss-of-Signal Response Time
fCLK tR tF Figure 3 Figure 3
2.4 -- -- 48
-- 70 70 50 80 80 230 230 -40 -30 -- --
2.7 90 90 52 110 110 265 265 -10 0 -- --
GHz ps ps % of UI ps ps ps
tR tF tCr-D
Figure 3 Figure 3 Figure 2
-- -- 190 190
tCf-D
Figure 2 -70 -60 100 kHz-1.5 GHz 1.5 GHz-4.0 GHz -15 -10 ps dB dB
VSLICE
SLICE_LVL = 750 mV to 2.25 V LOS_LVL = 1.50 to 2.50 V Figure 5 0 8
See Figure 8 on page 14.
VLOS tLOS
-- 20
40 25
mV s
*Note: Adjustment voltage is calculated as follows: VLOS = (LOS_LVL - 1.50)/25.
8
Rev. 1.4
SI5017
Table 4. AC Characteristics (PLL Characteristics)
(VDD =3.3 V 5%, TA = -40 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance (OC-48)*
JTOL(PP)
f = 600 Hz f = 6000 Hz f = 100 kHz f = 1 MHz
40 4 3 0.3 -- -- -- --
-- -- -- -- 3.0 25 -- 0.03 1.6 100 2.0 2.5 155.52 77.76 19.44 -- 650
-- -- -- -- 5.0 55 2.0 0.1 2.2 500 5.5 5.5 -- -- -- +500 --
UIPP UIPP UIPP UIPP mUI mUI MHz dB ms s ms ms
RMS Jitter Generation* Peak-to-Peak Jitter Generation Jitter Transfer Bandwidth* Jitter Transfer Peaking
* *
JGEN(rms) JGEN(PP) JBW JP TAQ
with no jitter on serial data with no jitter on serial data OC-48
Acquisition Time (Reference clock applied)
After falling edge of RESET/CAL From the return of valid data
-- 20 -- 1.5 -- -- -- -500 --
Acquisition Time (Reference-less operation)
TAQ
After falling edge of RESET/CAL From the return of valid data
Reference Clock Range See Table 7 on page 13. Input Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) CTOL
fCLK / 16 fCLK / 32 fCLK / 128
MHz ppm ppm
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 - 1 data pattern.
9
Rev. 1.4
SI5017
Table 5. Absolute Maximum Ratings
Parameter Symbol Value Unit
DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 k)
VDD VDIG VDIF
-0.5 to 3.5 -0.3 to 3.6 -0.3 to (VDD+ 0.3) 50
V V V mA C C kV
TJCT TSTG
-55 to 150 -55 to 150 1
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter Symbol JA Test Condition Value Unit
Thermal Resistance Junction to Ambient
Still Air
38
C/W
10
Rev. 1.4
SI5017
3. Typical Application Schematic
LVTTL BER Alarm Loss-of-Signal Control Inputs Indicator Indicator Loss-of-Lock Indicator
LTR
CLKDSBL
RESET/CAL
DSQLCH
LOL
High-Speed Serial Input System Reference Clock (Optional)
DIN+ DIN- REFCLK+ REFCLK-
BER_ALM
DOUT+ DOUT-
LOS
Recovered Data
SI5017
CLKOUT+ CLKOUT-
Recovered Clock
SLICE_LVL
BER_LVL
LOS_LVL
REXT
10 k (1%) Loss-of-Signal Data Slice Level Set Level Set Bit Error Rate Level Set
100 pF x 4
VDD 0.1 F
Rev. 1.4
GND
VDD
11
SI5017
4. Functional Description
The SI5017 integrates a high-speed limiting amplifier with a CDR unit that operates between 2.4 and 2.7 Gbps. No external reference clock is required for clock and data recovery. The limiting amplifier magnifies very low-level input data signals so accurate clock and data recovery can be performed. The CDR uses Silicon Laboratories DSPLL(R) technology to recover a clock synchronous to the input data stream. The recovered clock retimes the incoming data, and both are output synchronously via current-mode logic (CML) drivers. Silicon Laboratories' DSPLL technology ensures superior jitter performance while eliminating the need for external loop filter components found in traditional phase-locked loop (PLL) implementations. The limiting amplifier includes a control input for adjusting the data slicing level and provides a loss-ofsignal level alarm output. The CDR includes a bit-errorrate performance monitor which signals a high bit-errorrate condition (associated with excessive incoming jitter) relative to an externally adjustable bit-error-rate threshold. The optional reference clock minimizes the CDR acquisition time and provides a stable reference for maintaining the output clock when locking to reference is desired. traditional methods, and it eliminates performance degradation caused by external component aging. In addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources and making SONET/SDH jitter compliance easier to attain in the application.
4.3. Operation Without an External Reference
The SI5017 can perform clock and data recovery without an external reference clock. Tying the REFCLK+ input to VDD and the REFCLK- input to GND configures the device to operate without an external reference clock. Clock recovery is achieved by monitoring the timing quality of the incoming data relative to the VCO frequency. Lock is maintained by continuously monitoring the incoming data timing quality and adjusting the VCO accordingly. Details of the lock detection and the lock-to-reference functions while in this mode are described in their respective sections below.
Note: Without an external reference the acquisition of data is dependent solely on the data itself and typically requires more time to acquire lock than when a reference is applied.
4.4. Operation With an External Reference
The SI5017 can also perform clock and data recovery with an external reference. The device's optional external reference clock centers the DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the SI5017 uses the reference clock to center the VCO output frequency so that clock and data are recovered from the input data stream. The device self configures for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The reference clock centers the VCO for a nominal output between 2.5 and 2.7 GHz. The VCO frequency is centered at 16, 32, or 128 times the reference clock frequency. Detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal VCO output. Approximate reference clock frequencies for some target applications are given in Table 7.
4.1. Limiting Amplifier
The limiting amplifier accepts the low-level signal output from a transimpedance amplifier (TIA). The low-level signal is amplified to a usable level for the CDR unit. The minimum input swing requirement is specified in Table 2. Larger input amplitudes (up to the maximum input swing specified in Table 2) are accommodated without degradation of performance. The limiting amplifier ensures optimal data slicing by using a digital dc offset cancellation technique to remove any dc bias introduced by the amplification stage.
4.2. DSPLL(R)
The SI5017 PLL structure (shown in the "Detailed Block Diagram" on page 4) utilizes Silicon Laboratories' DSPLL technology to maintain superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). This technology enables CDR with far less jitter than is generated using
12
Rev. 1.4
SI5017
Table 7. Typical REFCLK Frequencies
SONET/SDH OC-48 with Ratio of VCO 15/14 FEC to REFCLK
19.44 MHz 77.76 MHz
20.83 MHz 83.31 MHz
128 32 16
of LTR forces the DSPLL to lock CLKOUT to the provided reference. If no external reference clock is used, LTR forces the DSPLL to hold the digital frequency control input to the VCO at the last value. This produces a stable output clock as long as supply and temperature are constant.
4.7. Loss-of-Signal (LOS)
The SI5017 indicates a loss-of-signal condition on the LOS output pin when the input peak-to-peak signal level on DIN falls below an externally controlled threshold. The LOS threshold range is specified in Table 3 and is set by applying a voltage on the LOS_LVL pin. The graph in Figure 6 illustrates the LOS_LVL mapping to the LOS threshold. The LOS output is asserted when the input signal drops below the programmed peak-topeak value. If desired, the LOS function may be disabled by grounding LOS_LVL or by adjusting LOS_LVL to be less than 1 V.
Note: The LOS circuit is designed to only work with pseudorandom, dc-balanced data.
155.52 MHz 166.63 MHz
4.5. Lock Detect
The SI5017 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The operation of the lock-detector depends on the reference clock option used. When an external reference clock is provided, the circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 9, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. In this state, the PLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (CLKOUT) drifts over a 600 ppm range relative to the applied reference clock and the LOL output alarm may toggle until the PLL has reacquired frequency lock. Due to the low noise and stability of the DSPLL, there is the possibility that the PLL will not drift enough to render an out-of-lock condition, even if the data is removed from inputs. In applications requiring a more stable output clock during out-of-lock conditions, the lock-to-reference (LTR) input can be used to force the PLL to lock to the externally supplied reference. In the absence of an external reference, the lock detect circuitry uses a data quality measure to determine when frequency lock has been lost with the incoming data stream. During reacquisition, CLKOUT may vary by approximately 10% from the nominal data rate.
40 mV
LOS Threshold (mVPP)
30 mV
LOS Disabled
15 mV
LOS Undefined
40mV/V
0 mV 0V 1.00 V 1.50 V
LOS Limited by Device Noise
1.875 V
2.25 V
2.50 V
LOS_LVL (V)
Figure 6. LOS_LVL Mapping
R1
3
LOS_LVL SI5017 CDR LOS 9
LOS Alarm
Set LOS Level
R2 10k
4.6. Lock-to-Reference
The LTR input is used to force a stable output clock when an alarm condition, like LOS, exists. In typical applications, the LOS output is tied to the LTR input to force a stable output clock when the input data signal is lost. When LTR is asserted, the DSPLL is prevented from acquiring the data signal present on DIN. The operation of the LTR control input depends on which reference clocking mode is used. When an external reference clock is present, assertion
Figure 7. LOS Signal Hysteresis
13
Rev. 1.4
SI5017
In many applications it is desirable to produce a fixed amount of signal hysteresis for an alarm indicator such as LOS, since a marginal data input signal could cause intermittent toggling, leading to false alarm status. When it is anticipated that very low-level DIN signals will be encountered, the introduction of an adequate amount of LOS hysteresis is recommended to minimize any undesirable LOS signal toggling. Figure 7 illustrates a simple circuit that may be used to set a fixed level of LOS signal hysteresis for the SI5017 CDR. The value of R1 may be chosen to provide a range of hysteresis from 3 to 8 dB where a nominal value of 800 adjusts the hysteresis level to approximately 6 dB. Use a value of 500 or 1000 for R1 to provide 3 dB or 8 dB of hysteresis, respectively. Hysteresis is defined as the ratio of the LOS deassert level (LOSD) and the LOS assert level (LOSA). The hysteresis in decibels is calculated as 20log(LOSD/ LOSA). of the expected event window are counted as bit errors. The BER threshold is programmed by applying a voltage to the BER_LVL pin between 500 mV and 2.25 V corresponding to a BER of approximately 10-10 and 10-6, respectively. The voltage present on BER_LVL maps to the BER as follows: log10(BER) = (4 x BER_LVL) - 13. (BER_LVL is in volts; BER is in bits per second.).
4.9. Data Slicing Level
The SI5017 provides the ability to externally adjust the slicing level for applications that require bit-error-rate (BER) optimization. Adjustments in slicing level of 25 mV (typical, relative to the internally set input common mode voltage) are supported. The slicing level is set by applying a voltage between 0.75 and 2.25 V to the SLICE_LVL input. See Figure 8 for the operation levels of the slice circuit. When SLICE_LVL is driven below 500 mV, the slicing level adjustment is disabled, and the slicing level is set to the cross-point of the differential input signal.
Note: The slice circuit is designed to only work with pseudorandom, dc-balanced data.
4.8. Bit-Error-Rate (BER) Detection
The SI5017 uses a proprietary Silicon Laboratories algorithm to generate a bit-error-rate (BER) alarm on the BER_ALM pin if the observed BER is greater than a user programmable threshold. Bit error detection relies on the input data edge timing; edges occurring outside
40 30
Not Specified
Slice Disable
20 10 0 -10 -20 -30 -40 0.00
10 mV
10 mV
Note: SLICE is a continuous curve. This chart shows the range of results from part-to-part.
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
Figure 8. SI5017 OC-48 Slice Specification
14
Rev. 1.4
SI5017
4.10. PLL Performance
The PLL implementation used in the SI5017 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958.
4.10.1. Jitter Tolerance
The SI5017's tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 8. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device.
4.10.2. Jitter Transfer
the DSPLL on powerup. Calibration may also be initiated by a high-to-low transition on the RESET/CAL pin. The RESET/CAL pin must be held high for at least 1 s. When RESET/CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL, and begins to lock to the incoming data stream. For a valid reset to occur when using Reference mode, a proper, external reference clock frequency must be applied as specified in Table 7.
4.12. Clock Disable
The SI5017 provides a clock disable pin (CLK_DSBL) that is used to disable the recovered clock output (CLKOUT). When the CLK_DSBL pin is asserted, the positive and negative terminals of CLKOUT are tied to VDD through 100 on-chip resistors.
The SI5017 exceeds all relevant Bellcore/ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency. These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 9.
Jitter Transfer
4.13. Data Squelch
The SI5017 provides a data squelching pin (DSQLCH) that is used to set the recovered data output (DOUT) to binary zero. When the DSQLCH pin is asserted, the DOUT+ signal is held low and the DOUT- signal is held high. This pin can be is used to squelch corrupt data during LOS and LOL situations. Care must be taken when ac coupling these outputs; a long string of zeros or ones will not be held through ac coupling capacitors.
0.1 dB
20 dB/Decade Slope Acceptable Range
4.14. Device Grounding
The SI5017 uses the GND pad on the bottom of the 28pin micro leaded package (QFN) for device ground. This pad should be connected directly to the analog supply ground. See Figure 15 on page 19 and Figure 16 on page 23 for the ground (GND) pad location.
Fc Frequency SONET Data Rate OC-48 Fc (kHz) 2000
4.15. Bias Generation Circuitry
The SI5017 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 k (1%) resistor connected between REXT and GND.
Figure 9. Jitter Transfer Specification
4.10.3. Jitter Generation
The SI5017 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The SI5017 typically generates less than 3.0 mUIrms of jitter when presented with jitter-free input data.
4.16. Voltage Regulator
The SI5017 operates from a 3.3 V external supply voltage. Internally the device operates from a 2.5 V supply. The SI5017 regulates 2.5 V internally down from the external 3.3 V supply. In addition to supporting 3.3 V systems, the on-chip linear regulator offers better power supply noise rejection versus a direct 2.5 V supply.
4.11. RESET/DSPLL Calibration
The SI5017 achieves optimal jitter performance by automatically calibrating the loop gain parameters within
15
Rev. 1.4
SI5017
4.17. Differential Input Circuitry
The SI5017 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figures 10 and 11, respectively. In applications where direct dc coupling is possible, the 0.1 F capacitors may be omitted. (LOS operation is only guaranteed when ac coupled.) The data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as specified in Table 2 on page 7 to ensure a BER of at least 10-12. The REFCLK input differential peak-to-peak voltage requirement is also specified in Table 2.
SI5017 Clock source
2.5 k 0.1 F Zo = 50 RFCLK + 10 k 2.5 k
2.5 V (5%)
100 0.1 F Zo = 50 RFCLK -
10 k
GND
Figure 10. Input Termination for REFCLK (ac coupled)
TIA
0.1 F Zo = 50
SI5017
2.5 V (5%)
DIN+
50
5 k
0.1 F
50 Zo = 50 DIN-
7.5 k
GND
Figure 11. Input Termination for DIN (ac coupled)
16
Rev. 1.4
SI5017
SI5017 2.5 V (5%)
2.5 k 0.1 F Zo = 50 RFCLK + 10 k 50 RFCLK - 10 k 0.1 F 2.5 k
Clock source
GND
Figure 12. Single-Ended Input Termination for REFCLK (ac coupled)
Signal source
0.1 F Zo = 50 DIN+
SI5017
2.5 V (5%)
50 100 50 DIN-
5 k
7.5 k
0.1 F
GND
Figure 13. Single-Ended Input Termination for DIN (ac coupled)
17
Rev. 1.4
SI5017
4.18. Differential Output Circuitry
The SI5017 utilizes a CML architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 on page 7.
SI5017 2.5 V (5%)
100
VDD
50
DOUT+, CLKOUT+
0.1 F
Zo = 50
DOUT-, CLKOUT-
0.1 F
Zo = 50
100
2.5 V (5%)
50
VDD
Figure 14. Output Termination for DOUT and CLKOUT (ac coupled)
18
Rev. 1.4
SI5017
5. Pin Descriptions: SI5017
BER_ALM CLKOUT+ DIN- CLKOUT- 21 VDD 20 REXT 19 RESET/CAL 18 VDD 17 DOUT+ 16 DOUT- 15 TDI 8 LTR 9 LOS 10 11 12 13 14 DSQLCH VDD DIN+ VDD CLKDSBL BER_LVL
28 27 26 25 24 23 22 VDD VDD LOS_LVL SLICE_LVL REFCLK+ REFCLK- LOL 1 2 3 4 5 6 7
GND Pad
Figure 15. SI5017 Pin Configuration Table 8. SI5017 Pin Descriptions
Pin # Pin Name I/O Signal Level Description Supply Voltage. Nominally 3.3 V. LOS Level Control. The LOS threshold is set by the input voltage level applied to this pin. Figure 6 on page 13 shows the input setting to output threshold mapping. LOS is disabled when the voltage applied is less than 1 V. Slicing Level Control. The slicing threshold level is set by applying a voltage to this pin as described in the Slicing Level section of the data sheet. If this pin is tied to GND, slicing level adjustment is disabled, and the slicing level is set to the midpoint of the differential input signal on DIN. Slicing level becomes active when the voltage applied to the pin is greater than 500 mV.
1,2,11,14,18, 21,25 3
VDD LOS_LVL I
3.3 V
4
SLICE_LVL
I
5 6
REFCLK+ REFCLK-
I
See Table 2
VDD
NC
Differential Reference Clock (Optional). When present, the reference clock sets the center operating frequency of the DSPLL for clock and data recovery. Tie REFCLK+ to VDD and REFCLK- to GND to operate without an external reference clock. See Table 7 on page 13 for typical reference clock frequencies.
Rev. 1.4
19
SI5017
Table 8. SI5017 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 9. If no external reference is supplied, this signal will be active when the internal PLL is no longer locked to the incoming data. Lock-to-Reference. When this pin is low, the DSPLL disregards the data inputs. If an external reference is supplied, the output clock locks to the supplied reference. If no external reference is used, the DSPLL locks the control loop until LTR is released.
Note: This input has a weak internal pullup.
7
LOL
O
LVTTL
8
LTR
I
LVTTL
9
LOS
O
LVTTL
Loss-of-Signal. This output pin is driven low when the input signal is below the threshold set via LOS_LVL. (LOS operation is guaranteed only when ac coupling is used on the DIN inputs.) Data Squelch. When driven high, this pin forces the data present on DOUT+ to zero and DOUT- to one. For normal operation, this pin should be low. DSQLCH may be used during LOS/LOL conditions to prevent random data from being presented to the system.
Note: This input has a weak internal pulldown.
10
DSQLCH
LVTTL
12 13
DIN+ DIN-
I
See Table 2
Differential Data Input. Clock and data are recovered from the differential signal present on these pins. AC coupling is recommended. Production Test Input. This pin is used during production testing and must be tied to GND for normal operation. Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. Reset/Calibrate. Driving this input high for at least 1 s will reset internal device circuitry. A high to low transition on this pin will force a DSPLL calibration. For normal operation, drive this pin low.
Note: This input has a weak internal pulldown.
15
GND
GND
16 17 19
DOUT- DOUT+ RESET/CAL
O
CML
I
LVTTL
20
REXT
External Bias Resistor. This resistor is used to establish internal bias currents within the device. This pin must be connected to GND through a 10 k (1%) resistor.
20
Rev. 1.4
SI5017
Table 8. SI5017 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level Description Differential Clock Output. The output clock is recovered from the data signal present on DIN except when LTR is asserted or the LOL state has been entered. Clock Disable. When this input is high, the CLKOUT output drivers are disabled. For normal operation, this pin should be low.
Note: This input has a weak internal pulldown.
22 23
CLKOUT- CLKOUT+
O
CML
24
CLKDSBL
I
LVTTL
26
BER_LVL
I
Bit Error Rate Level Control. The BER threshold level is set by applying a voltage to this pin. When the BER exceeds the programmed threshold, BER_ALM is driven low. If this pin is tied to GND, BER_ALM is disabled.
27
BER_ALM
O
LVTTL
Bit Error Rate Alarm. This pin will be driven low to indicate that the BER threshold set by BER_LVL has been exceeded. There is no hysteresis. No Connect. Leave this pin disconnected.
28 GND Pad
NC GND GND
Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 28-lead QFN (see Figure 16 on page 23) must be connected directly to supply ground. Minimize the ground path inductance for optimal performance.
Rev. 1.4
21
SI5017
6. Ordering Guide
Part Number Package Voltage Lead-Free Temperature
SI5017-X-GM
28-Lead QFN
3.3
Yes
-40 to 85 C
1. "X" denotes product revision. 2. Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel.
22
Rev. 1.4
SI5017
7. Package Outline
Figure 16 illustrates the package details for the SI5017. Table 9 lists the values for the dimensions shown in the illustration.
2X 0.10 C A A D D/2 D1 D1/2 N 1 2 3 2X 0.10 C B A A1 0.05 C b D2 N 1 2 3 E E2 (Ne-1) Xe REF. 0.10
M
CAB
E1/2 E1
E/2
L B
TOP VIEW
C
SEATING PLANE
e (Nd-1) Xe REF.
CCC L
b
A1
BOTTOM VIEW
SECTION "C-C"
e SCALE: NONE
Approximate device weight is 62.2 mg.
Figure 16. 28-Lead Quad Flat No-Lead (QFN) Table 9. Package Diagram Dimensions
Controlling Dimension: mm Symbol Millimeters Min Nom A -- 0.85 A1 0.00 0.01 b 0.18 0.23 D 5.00 BSC D1 4.75 BSC D2 2.95 3.10 E 5.00 BSC E1 4.75 BSC E2 2.95 3.10 N 28 Nd 7 Ne 7 e 0.50 BSC L 0.50 0.60
Max 0.90 0.05 0.30
3.25
3.25
0.75 12
Rev. 1.4
23
SI5017
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
Added Figure 4, "PLL Acquisition Time," on page 6. Table 2 on page 7
Added FEC (2.7 GHz) Supply Current Updated values: Supply Current Added FEC (2.7 GHz) Power Dissipation Updated values: Power Dissipation Updated values: Common Mode Input Voltage (REFCLK) Updated values: Output Common Mode Voltage
Updated Figure 16, "28-Lead Quad Flat No-Lead (QFN)," on page 23. Updated Table 9, "Package Diagram Dimensions," on page 23.
Changed dimension A. Changed dimension E2.
Revision 1.2 to Revision 1.3
Table 2 on page 7.
Updated power consumption. Updated RIN.
Table 3 on page 8.
Updated clock to data delay. Updated slicing level accuracy.
Table 3 on page 8
Added separate Output Clock Rise Time Added separate Output Clock Fall Time Updated values: Output Clock Rise Time Updated values: Output Clock Fall Time
Table 4 on page 9.
Updated tolerance. Updated acquisition time. Updated reference clock information.
Table 4 on page 9
Updated values: Jitter Tolerance (OC-48) for f = 1 MHz Updated values: Acquisition Time (reference clock applied) Updated values: Acquisition Time (reference-less operation) Updated values: Freq Difference at which Receive PLL goes out of Lock Updated values: Freq Difference at which Receive PLL goes into Lock
Updated "Ordering Guide" on page 22.
Added "X" to part number.
Revision 1.3 to Revision 1.4
Updated Table 2 on page 7.
Added limits for VICM. Updated VOD.
Updated Table 3 on page 8.
Updated TCr-D. Updated TCf-D. Revised SLICE specification.
Removed "Hysteresis Dependency" Figure. Added Figure 7, "LOS Signal Hysteresis," on page 13. Corrected error: Table 8 on page 19--changed description for LOS_LVL from "LOS is disabled when the voltage applied is less than 500 mV" to "LOS is disabled when the voltage applied is less than 1.0 V."
Updated Table 4 on page 9.
TAQ min/max values updated.
Updated "Loss-of-Signal (LOS)" on page 13.
Added note describing valid signal. Updated Figure 6, "LOS_LVL Mapping," on page 13.
Revision 1.0 to Revision 1.1
Corrected "Revision 0.1 to Revision 1.0" Change List.
Updated "Data Slicing Level" on page 14.
Added Figure 8 on page 14. Revised text.
Revision 1.1 to Revision 1.2
Added Figure 5, "LOS Response Time," on page 6. Updated Table 2 on page 7
Added "Output Common Mode Voltage (DOUT)" with updated values. Added "Output Common Mode Voltage (CLKOUT)" with updated values.
Table 3 on page 8.
Added "Output Clock Duty Cycle" Added "Loss-of-Signal Response Time"
Updated Table 8 on page 19
Changed "clock input" to "DIN inputs" for Loss-of-Signal.
24
Rev. 1.4
SI5017
NOTES:
Rev. 1.4
25
SI5017
CONTACT INFORMATION
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
26
Rev. 1.4

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